The basic element of all emitter coupled logic (ECL) gates or current mode logic (CML) gates is a differential amplifier. Therefore, there is a significant incentive to .fine tune the operation of the differential amplifier, thus improving the operation of the overall ECL or CML logic gate.
The differential amplifier typically has two emitter-coupled bipolar transistors; each having a resistive Icad coupled between their collectors and a power supply. The common emitters of the transistor pair are coupled to a current source. Both the resistive loads and current source are typically semiconductor resistors. However, it is also common to utilize a bipolar transistor that is biased in its linear region for the current source. The base of one of the emitter-coupled pair is coupled to a reference potential and the base of the other emitter-coupled transistor is coupled to an input signal.
The differential amplifier functions such that it compares the input signal to the reference potential. Depending on whether the input signal is less than or greater than the reference potential, the differential amplifier steers the current established by the current source through one of the emitter-coupled transistors. This current flow causes a corresponding voltage drop across only one of the load resistors. At the same time, because no current flows through the other transistor, the collector of that transistor remains at approximately ground potential. The output of the differential amplifier is typically taken at the collector of each of the emitter-couple coupled transistor. Thus one collector is always at a voltage potential corresponding to a low logic level and the other collector is at a voltage potential corresponding to a high logic level.
As is commonly known in the industry, ECL/CML gates are desirable because they provide the fastest bipolar logic available. However, the main drawback of the ECL/CML differential amplifier as described above is that they consume thee most power of conventional logic technologies and can be adversely affected by temperature and power supply variations.
One method of improving the operation of the differential amplifier described above is suggested in U.S. Pat. No. 5,124,580 assigned to the assignee of the present invention. U.S. Pat. No. 5,124,580 describes a bipolar complementary metal-oxide semiconductor (BiCMOS) ECL/CML gate. The basic bipolar ECL/CML gate is improved by replacing the current source comprising a resistive semiconductor with an MOS device biased to function as a current source, i.e. operated in its saturation region.
Further, the two load resistors coupled to the emitter-coupled pair are replaced by two linearly operated MOS devices. The MOS devices are coupled between the collector of each of the emitter-coupled pair and a power supply. Beth of the gates of the MOS load devices are coupled to a second common bias potential. The value of the load resistance for the MOS load devices is determined by the second bias potential and the size of the MOS devices. The advantage of utilizing a linearly operated MOS device is that their resistance can be easily adjusted by changing the potential applied to their gate, i.e. the second bias potential. In this manner, the effect of variations such as temperature and power supply on the ECL/CML logic gate output voltage can be offset by proper control of the bias potential on the gate of the MOS load devices.
U.S. patent application Ser. No. 842,922 which is the continuation-in-part of U.S. Pat. No. 5,124,580 and is also to the assignee of the present invention, discloses a further improvement to the basic bipolar ECL/CML gate. The BiCMOS ECL/CML gate disclosed in U.S. patent application Ser. No. 842,922 improves the linearity of the the MOS load resisters. In one disclosed embodiment a plurality of parallel MOS devices are coupled between the collector of each of the emittercoupled pair and the power supply. The gates of each of the devices are coupled to a switching network. The switching network determines if the gate of each of the parallel MOS load devices are coupled to a bias potential or a deactivating voltage. The parallel MOS devices are linearly biased such that the effective resistance of the parallel combination is determined by the number ad size of Icad devices coupled to the bias potential.
In both of the BiCMOS ECL/CML gates as disclosed in U.S. Pat. No. 5,124,580 and U.S. patent application Ser. No. 842,922 it is important that the MOS load devices and current sources remain biased at a particular operating point, (i.e. linear for the load devices and saturated for the current source). Consequently, the bias voltages supplied to the gates of these MOS devices need to remain constant over variations due to effects of temperature, supply voltage and process fluctuations.
U.S. Pat. No. 5,124,580 discloses a feedback circuit for supplying stable bias voltages to the gates of the load and current source MOS devices. The feedback circuit provides bias potentials such that the MOS devices remain biased at their respective operating points independent of fluctuations in varying operating conditions. In addition, the feedback circuit allows the added advantage of having the ability of adjusting the voltage swing of the output of the ECL gate.
In a large logic circuit containing many logic gates it is desirable to provide compensated bias voltages to each gate. This would require the inclusion of a feedback circuit, as described above, in the design of each logic gate. However, each feedback circuit includes an operational amplifier and other space consuming circuitry. As a result, including a feedback circuit with each logic gate may not lend itself to a space efficient logic circuit design. In addition, adding the feedback circuitry may become prohibitive in some cases where minimal space is available. What is needed is a space efficient means for providing bias potentials for a BiCMOS ECL/CML logic gate that ensures that specific operating points are maintained for MOS load and current source devices.